The invention relates to a circuit arrangement for deriving the measured variable from the signals of at least two sensors of a flow meter, which flow meter comprises a fluid line or several parallel fluid lines and means for exciting oscillations of a predetermined fundamental frequency in the fluid line(s), the sensors detecting the oscillations and the sensor signals being supplied by way of a respective A-D converter to a digital processing unit having a computation circuit in which their phase difference is determined as a measure of the flow.
DE 43 19 344 C2 discloses a method of measuring the phase difference in a Coriolis mass flow meter. In this case, sensor signals representing physical variables of the flow, the phase difference of which signals is to be determined as a measure of the flow, are transmitted by way of amplifiers, analogue low-pass filters and analogue-to-digital converters to a processing unit, in which the phase difference is calculated.
U.S. Pat. No. 5,555,190 discloses a circuit arrangement of the kind mentioned initially for a Coriolis flow meter in which two tubes are caused to oscillate in anti-phase. The oscillations are measured by sensors at different points of the tubes, the phase difference between the sensor signals being used as a measure of the flow. For that purpose, the circuit arrangement contains two channels, in each of which there is arranged an analogue-to-digital converter having downstream thereof a so-called xe2x80x9cdecimatorxe2x80x9d, wherein the signals are subsequently passed through a digital rejection filter which allows all interference signals through apart from in a narrow stop frequency band around the fundamental frequency. This digitally filtered signal is subtracted from the original signal, in order to obtain a more accurate representation of the sensor signals. The stop frequency band of the filter is adjustable, the filter being controlled in accordance with an algorithm in such a way that it follows the changes in the fundamental frequency.
This method is suitable for measuring very small phase differences that occur in a Coriolis flow meter. The fundamental frequency of a flow meter is not constant, however. It is supposed to be changed in dependence on changes in the material properties of the tube and in the density of the fluid flowing through the flow meter. When the fundamental frequency is changed, the constants of the filter also have to be changed, in order to match the filter to the fundamental frequency. Changing of the filter constants produces a change in the output signal of the filter. A sudden change causes disturbance that falsifies the measurement signal. Only when the quiescent state has been reached, after matching to the fundamental frequency, do the measurements become reliable. In the interim period, they are seriously distorted and useless, and the measured flow is error-prone. That is why this method is not suitable for flow meters in which the fundamental frequency changes during operation.
U.S. Pat. No. 5,142,286 discloses an X-ray scintillator which has sigma-to-delta converters, downstream of which a so-called Hogenauer decimator is connected. The sigma-to-delta converters convert the analogue input signal at a high over-sampling frequency into a high-frequency digital signal. The downstream Hogenauer decimator scales down the sampling frequency of its input signal and suppresses high-frequency interference signals which occur during digitization.
From EP 0 282 552 it is known to extract phase difference between two sinusoidal signals by sampling a fixed number of times per cycle, multiply the samples with corresponding sine and cosine values and add the results for one whole cycle. The results represent the real and imaginary parts of the signal, and the tangent to the phase angle can be found by dividing the imaginary part with the real part. This method requires however, that the sampling is synchronized to multiples of the sensor frequency and it requires analog circuitry to change the clock frequency.
The invention is based on the problem of providing a circuit arrangement of the kind mentioned in the preamble, which allows a more accurate detection of the flow regardless of changes in the fundamental frequency, combined with a simple construction.
In accordance with the invention, that problem is solved in that the processing unit between the A-D converter of each sensor signal and the computation circuit comprises a digital multiplier circuit and a digital filter arrangement downstream thereof, the digital sensor signals are multiplied in the multiplier circuit with respective digital signals phase-displaced by 90xc2x0 with respect to one another that represent sinusoidal oscillations of identical amplitude and a frequency that varies by a slight difference frequency from the fundamental frequency, and the pass band of the filter arrangement is matched to the difference frequency. A clock independent of the sensor frequency controls the sampling rate and subsequent down-sampled calculations. This eliminates the need for analog circuitry to synchronize the sampling to a multiple of the sensor frequency.
This construction of the circuit arrangement enables the flow to be accurately calculated from the sensor signals of the flow meter without a change in the fundamental frequency falsifying the measurement result. The parameters of the filter arrangement can remain constant even when the fundamental frequency changes, provided that the pass band corresponds to the maximum possible difference frequency. Owing to the fact that multiplication is effected with approximately the same frequency, the difference frequency is very much lower than the original frequency. This simplifies construction. The circuit arrangement is suitable both for mass flow meters and for electromagnetic flow meters and other flow meters in which the measured value is derived from the phase angle and amplitudes of two sinusoidal signals.
The filter arrangement can comprise band-pass filters for the product signals resulting from the multiplication. Preferably, however, it comprises low-pass filters, which are connected downstream of a respective multiplying element of the multiplier circuit.
The A-D converter preferably contains a sigma-to-delta converter and a decimator connected downstream thereof. This enables the analogue sensor signals to be converted with a simple construction at very high sampling frequency and with little digitizing noise, whilst simultaneously reducing the repetition rate of the binary values produced in digitization, for matching to a lower clock rate of the computation circuit whilst maintaining the high measurement accuracy.
The decimators can comprise a Hogenauer circuit having a first matrix of digital integrators, followed by a corresponding second matrix of digital differentiating elements. This circuit enables the frequency of the bit sequence from the sigma-to-delta converter to be reduced. Here, a multiple integration of the serial bit sequence is followed by a corresponding multiple differentiation with simultaneous frequency division into lower-frequency parallel bit sequences.
In detail, it is possible for the first matrix to consist of m columns and n rows of integrators, each of which comprises an adder having a first and a second summing input, a carry input, a summation output and a carry output, the summation outputs being connected in each case to the first summing input of a following adder of the same row and the carry outputs of the adders of the same columns being connected in each case to the carry input of the adder of the next-higher bit position, and each integrator comprising a flip-flop having a data input and at least one output, the signal being transferred from the data input to the output of the flip-flop when a clock pulse at a clock input of the flip-flop changes value, and the summation output of the adder of the relevant integrator being connected to the data input, and the output of the flip-flop being connected to the second summing input of the adder of the same integrator. In this connection, the entire first matrix can be constructed from comparatively few, simple gates (logic elements). All gates can be in the form of integrated circuits on a single chip, since multipliers and memory space for filter coefficients are not required. The integrator matrix can nevertheless operate at very high speed.
The second matrix can consist of m columns and n rows of differentiating elements, each of which comprises an adder having two summing inputs, a carry input, a summation output and a carry output, the summation outputs being connected to a respective first summing input of a following adder of the same row and the carry outputs of the adders of the same columns being connected to the respective carry input of the adder of the next-higher bit position, and each differentiating element comprising a flip-flop having a data input and at least one output, the signal being transferred inverted from the data input to the output of the flip-flop when a clock pulse at a clock input of the flip-flop changes value, the data input of the flip-flop being connected to the first summing input of the adder of the relevant differentiating element and the output of the flip-flop being connected to the second summing input of the adder of the same differentiating element. This construction allows the differentiating matrix to be constructed from adders that operate by using the inverse outputs of the flip-flops and allocating a binary 1 as subtractor to the carry inputs of the adders of the lowest position. The differentiating matrix can therefore also be constructed from simple gates without multipliers and memory space for coefficients. In addition, they can advantageously be formed on the same chip as the integrator matrix.
It is preferably arranged that, in the first column of the first matrix, the first summing inputs of the adders, except for the adder of the lowest bit position, are connected to a common input for a serial bit sequence. The least-significant bit is always 1, since the serial bit sequence from the sigma-to-delta converter is taken to be +1 or xe2x88x921. The higher-order bits supplied to the connected inputs of the higher-order adders have a sign prefix. Although three series-connected integrators produce a carry, this is not important when the adders operate for a subtraction with the two""s complement to 1 and there are sufficient bits to represent the largest number occurring at the output.
Parallel bit patterns for +1 and xe2x88x921 can be supplied to the inputs of the decimator in dependence on the instantaneous value for the serial bit sequence, xe2x88x921 being entered as the two""s complement to 1. Thus, only two values are entered, which represent the instantaneous logical output value of the sigma-to-delta converter. This value is entered in parallel, however, and during subsequent integration and differentiation the bit pattern is processed without loss of information.
The first input of the lowest placed adder is preferably allocated a binary 1. In this way, +1 and the two""s complement can be formed by an inversion of the serial bit sequence and by supplying the inverted bit sequence to the first input of the adder of the next-higher position of a column. +1 and xe2x88x921 are in this instance formed in a very simple manner.
In the lowest placed row of the first matrix, the carry inputs of the adders are allocated a binary 0.
In the lowest placed row of the second matrix, the carry inputs of the adders are allocated a binary 1. Thus, a 1 is added to the inverted output signal of the adders by using the inverse outputs of the flip-flops, which represent the one""s complement, so that the signal that is returned from the flip-flops to the second input of the adders represents the two""s complement, so that the adders operate as subtractors.
The first matrix can operate at a high clock rate, whereas the second matrix operates at a lower clock rate. The serial high-frequency bit sequence thus becomes a parallel low-frequency bit sequence. The subsequent signal-processing can then be performed by a microprocessor.
Instead of constructing the differentiating elements of the second matrix as separate components, it is alternatively possible to realize the second matrix as a microprocessor, which is programmed to execute the differentiations following the integration. This has the advantage that the signal frequency after integration of the digitized signal is reduced, so that a fast microprocessor can now operate in real time, yet still be of simple and inexpensive construction.
The parameters of the filter arrangement are preferably variable in dependence on the application of the flow meter. In this way, all signals formed by the multiplication of the sum frequency can be filtered out, so that only signals of the difference frequency remain.
The computation circuit can determine the phase difference of the sensor signals in a simple manner according to the relation   ϕ  =      arc    ⁢          xe2x80x83        ⁢    tan    ⁢          xe2x80x83        ⁢                  bc        -        ad                              a          ⁢                      xe2x80x83                    ⁢          c                +        bd            
in which a and b are the output signals of the filter arrangement after multiplication of the one sensor signal and c and d are the output signals of the filter arrangement after multiplication of the other sensor signal.